1. Field of the Invention
The present invention relates to a delay lock loop (hereinafter referred to as DLL) circuit for a semiconductor memory element which generates a synchronized internal clock signal by receiving an external clock signal as an input. More particularly, it relates to a DLL circuit for a semiconductor memory element which generates a clock signal having a very fast period in order to enhance speed of data being synchronized by a clock signal.
2. Description of the Prior Art
FIG. 1 is a block diagram of a conventional DLL circuit.
Referring to FIG. 1, the conventional DLL circuit includes: a receiver 1 for receiving an external clock signal as an input; a digital to time converter 2; a clock deliverer 3; a delay monitor portion 4; and an time to digital converter 5.
Operations of the conventional DLL circuit will now be described with reference to FIG. 2 showing a timing diagram of the conventional DLL circuit shown in FIG. 1.
First, if a cycle t=.tau., it is determined that T1=t.sub.REC, T2=t.sub.MON, T3=t.sub.DELI, T2=T1+T3, and T4=.tau.-T2=.tau.-t.sub.MON, where .tau. is an external clock period, t.sub.REC is a delay time of the receiver 1, and t.sub.DELI is a delay time of the clock deliverer 3. As shown in FIGS. 1 and 2, if a DLL locking signal is enabled at a `HIGH` section of a start pulse signal START, a stop pulse signal STOP is disabled at the `HIGH` section, and .tau.&gt;T1+T2+T3. That is, an external clock period .tau. should be longer than the total time including receiving time T1, transmitting time T2 and monitor delay time T3.
Where a semiconductor memory element requires a clock of a very fast period in order to enhance an operation speed, the conventional DLL circuit does not generate an appropriate pulse signal. Namely, if a pulse period of which .tau. is below 5 ns is determined to perform an I/O (input/output) operation over 200 MHz, it is difficult to determine operation timing such as shown in FIG. 2 with the conventional DLL circuit.